1. Field of the Invention
The invention relates to three-dimensional circuits and more particularly to the formation of three-dimensional circuits.
2. Background
Three-dimensional circuits are generally those in which active or passive circuit elements are formed over a surface of a planar substrate. A three-dimensional circuit typically interacts with circuit elements formed in a surface of a substrate. A typical monolithic integrated circuit has transistors and other structures formed at least in part in the substrate. A three-dimensional circuit may rely, for example, for signal operation or function on a substrate, but the operation of the circuit elements do not utilize a portion of the substrate. Implementation of three-dimensional circuit arrays include, but are not limited to, memory arrays, resistor arrays, and transistor arrays.
Commonly-owned, U.S. Pat. No. 6,034,882 titled xe2x80x9cVertically Stacked Field Programmable Nonvolatile Memory and Method of Fabricationxe2x80x9d and co-pending U.S. patent application Ser. No. 09/560,626, titled xe2x80x9cThree-Dimensional Memory Array Method of Fabrication,xe2x80x9d describes, in one aspect, three-dimensional circuit arrays such as field programmable, nonvolatile memory arrays wherein circuits are fabricated in a vertical arrangement over rather than in a surface of a planar substrate, such as, for example, a semiconductor substrate.
In many instances, it is desirable from a processing standpoint to construct circuit arrays of multiple levels of similar materials. However, processing techniques such as cell definition through etch patterning often rely on materials of different composition to achieve desired patterning. Thus, what is needed are techniques for forming circuit arrays of similar material that offer consistent performance and distinguishable patterning avenues suitable for use in three dimensional circuit arrays.
The invention provides a technique for patterning circuit structures, including a technique wherein multiple layers of similar material may be selectively patterned to create desired structures.
In one embodiment, the method includes introducing a circuit structure over a substrate in a stacked configuration between a first level of signal line material and a second level of signal line material. The first and second levels of signal line material comprise similar material. The method also includes selectively patterning the second level of signal line material and at least part of the circuit structure, without patterning the first level of signal line material. In this manner, the invention provides a technique wherein multiple signal lines of similar material coupling a respective plurality of circuit levels may be incorporated and patterned sequentially without concern of disruption or damage to previously introduced and patterned signal lines.
One way the second signal line material is patterned exclusive of the first signal line material is by modifying the etch chemistry from a first chemistry that favors the etching of signal line material (e.g., second signal line material) to a second chemistry that disfavors the etching of signal line material prior to contacting, for example, the first signal line material.
A second way the second signal line material is patterned exclusive of the first signal line material is by including an etch stop between the first and second signal line material. Examples of suitable etch stop materials include, but are not limited to, materials that are transient or temporary in that, for example, the material may be removed or changed with subsequent processing (e.g., thermal processing). Alternatively, the etch stop material may form part of the three-dimensional circuit structure between the first and second signal line materials.
The invention also describes a technique for patterning a desired edge angle by modifying, for example, an etch chemistry between a first chemistry that is generally anisotropic and a second chemistry that has a horizontal component. According to this example, an edge angle that is slightly re-entrant (i.e., has a negative slope) may be realized.
Additional features, embodiments, and benefits will be evident in view of the figures and detailed description presented herein.